IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures

ABSTRACT

An IC package including an integrated circuit die having a major surface and one or more solder bumps located on the major surface in at least one corner region of the major surface and a substrate having a surface, the surface including bump pads thereon. The major surface of the integrated circuit die faces the substrate surface, the one or more solder bumps are bonded to individual ones of the bump pads to thereby form a bond joint, the major surface of the integrated circuit die has a footprint area of at least about 400 mm 2 . A ratio of a coefficient of thermal expansion of the substrate (CTE sub ) to a coefficient of thermal expansion of the integrated circuit die (CTE die ) is at least about 3:1. A method of manufacturing an IC package is also disclosed.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.16/553,962, entitled “IC PACKAGE DESIGN AND METHODOLOGY TO COMPENSATEFOR DIE-SUBSTRATE CTE MISMATCH AT REFLOW TEMPERATURES”, filed Aug. 28,2019. The above-listed application is commonly assigned with the presentapplication is incorporated herein by reference as if reproduced hereinin its entirety.

TECHNICAL FIELD

This application is directed, in general, to integrated circuit packagesand methods of manufacturing thereof.

BACKGROUND

Improvements in integrated circuit (IC) fabrication techniques allow theproduction of larger area dies (IC dies) to accommodate higher densitiesof transistor devices therein. This, in turn, places an increasingdemand on packaging techniques to provide an increased number of alignedelectrical connections between the die and the substrate (IC packagesubstrate). As the density of connections between the die and thesubstrate increase, differences in the thermal properties of the die andIC package take on added importance.

SUMMARY

One aspect of the present disclosure provides an integrated circuitpackage including an integrated circuit die having a major surface andone or more solder bumps located on the major surface in at least onecorner region of the major surface and a substrate having a surface, thesurface including bump pads thereon. The major surface of the integratedcircuit die faces the substrate surface, the one or more solder bumpsare bonded to individual ones of the bump pads to thereby form a bondjoint, the major surface of the integrated circuit die has a footprintarea of at least about 400 mm². A ratio of a coefficient of thermalexpansion of the substrate (CTE_(sub)) to a coefficient of thermalexpansion of the integrated circuit die (CTE_(die)) is at least about3:1

In another aspect, a method of manufacturing an IC package is disclosed.The method includes providing a test one of an integrated circuit diehaving a major surface and a solder bump located on the major surfaceand providing a test one of a substrate having a surface, the surfaceincluding a bump pad located thereon. The bump pad is at a location onthe surface for alignment and bonding to the solder bump when the die ispositioned at a target mounting location relative to the substrate withthe die and the substrate at room temperature. The method also includesdetermining a shrinkage factor (SF) for the bump pad according to theformula: SF=1−(ΔD_(offset)/D_(rt)). D_(rt) is a distance between acenter of the die and a center of the solder bump with the solder bumpand the bump pad aligned with each other and the die at the targetmounting location at room temperature.ΔD_(offset)=|D_(substrate reflow)−D_(pad reflow)|. D_(substrate reflow)is a lateral offset distance between the center of die. D_(pad reflow)is an offset distance between the center of the die and the solder bump,with the die positioned at the target mounting location and with thetest die and the test substrate at an alignment reflow temperature forbonding the solder bump to the bump pad. The method further includesforming another of the bump pad on the surface of a production one ofthe substrate, wherein the location of the bump pad on the productionsubstrate is offset by the shrinkage factor multiplied by the bump padlocation on the test substrate such that a lateral distance between acenter of the die and the bump pad on the production substrate at roomtemperature equals SF×D_(rt). The method also includes positioning aproduction one of the integrated circuit die and the productionsubstrate such that a production one of the solder bump on the majorsurface of the production integrated circuit die faces the productionsubstrate surface at the target mounting location. The method furtherincludes forming a bond joint between the production solder bump and theproduction bump pad, the forming including applying a heat reflow cycleto the production die and the production substrate.

BRIEF DESCRIPTION

Reference is now made to the following descriptions taken in conjunctionwith the accompanying drawings, in which:

FIG. 1 presents a plan view of an example embodiment of an IC packagemanufactured according to the principles of the disclosure;

FIG. 2 present a cross-sectional detail view of a solder bump and bumppad of an example embodiment of an IC package, similar to the IC packagediscussed in the context of FIG. 1;

FIG. 3 presents a flow diagram of example embodiments of a method ofmanufacturing an IC package according to the principles of thedisclosure, including any of the package embodiments, such as disclosedin the context of FIGS. 1 and 2; and

FIGS. 4A-4D show cross-sectional views analogous to that shown in FIG. 2for example embodiments of test and production dies and substrates atselected stages of the method, such as disclosed in the context of FIG.3.

DETAILED DESCRIPTION

We present a solution to new challenges of achieving improved solderbump-bump pad alignment in IC packages, including packages using largerarea dies (e.g., die areas equal to greater than about 400 mm²) toaccommodate more complex circuitry, including an increasing pitchdensity of solder bumps and/or decreasing diameters of solder bumps andcorresponding bump pads. For such dies, when there is a large differencein the coefficient of thermal expansion of the die (CTE_(die)) andsubstrate (CTE_(sub)), the precise alignment and thermal bonding betweenthe solder bumps of the die and the bump pads of the substrate canbecome difficult to achieve, due to large differences in the relativeexpansion of the die and the substrate during thermal heat cycling.

Consider, for example, a die and substrate having a CTE_(die) andCTE_(sub) equal to about 3 and 12 ppm/° C. respectively, and the diepositioned at a mounting position relative to the substrate such that,at room temperature (25° C.), a solder bump on the die is aligned with abump pad on the substrate. During a heating reflow cycle to create asolder bond joint, the substrate, due to its higher CTE, will expandmore than the die thereby causing misalignment between the solder bumpand the bump pad. If the misalignment is great enough, the solder bondjoint may not form, or, if the misalignment is partial, the solder bondjoint forms but the misalignment is sufficient that the canted or tiltedbond joint may be prone to cracking, during use or during a thermalcycling test to evaluate bond joint integrity, due to internal stresses.

As further disclosed herein, we have developed a shrinkage factor, thatwhen applied, adjusts the planned location of the bump pad on thesubstrate such that, at room temperature, the bump pad is offsetrelative to its corresponding solder bump on the die. The shrinkagefactor accounts for the differences in CTE_(die) and CTE_(sub) such thatthe bump pads and solder bumps will become aligned during a thermal heatcycle such that solder bump and bump pad are substantially aligned andthereby form a solder bond joint that can maintain integrity during athermal cycling test.

This is in contrast to some previous flip chip bonding processes wherethe bump pads are positioned on the substrate such that there is a zerooffset relative to their corresponding solder bumps at room temperature.Consequently, during heating reflow cycle the locations of the solderbumps and bump pads become misaligned due to the differences inCTE_(die) and CTE_(sub). We believe that, while for smaller area dies(e.g., die areas of less than 400 mm²) and larger solder bump and bumppad diameters (e.g., greater than 200 μm), a degree of misalignmentduring the thermal heat cycle can be tolerated with the solder bondjoint still being formed, larger area dies are surprisingly intolerantto misalignment, especially in perimeter regions of the die such ascorner regions of the die.

One aspect of the disclosure is an integrated circuit package. FIG. 1illustrates a plan view of an embodiment of an example IC package 100constructed according to the principles of the disclosure. FIG. 2illustrates a cross-sectional detailed view a solder bump and bump padpair for an embodiment of an example IC package 100, similar to the ICpackage illustrated in FIG. 1.

With continuing reference to FIGS. 1-2 throughout, embodiments of theintegrated circuit package 100 can include an integrated circuit die 105having a major surface 110 and one or more solder bumps 115 located onthe major surface 110 in at least one corner region 120 of the majorsurface 110. The package 100 can also include a substrate 125 having asurface 130, the surface 130 including bump pads 135 thereon. The majorsurface 110 of the integrated circuit die 105 faces the substratesurface 130. The one or more solder bumps 115 are bonded to individualones of the bump pads 135 to thereby form a bond joint 202. The majorsurface of the integrated circuit die has a footprint area (e.g.,defined by perimeter 145) of at least about 400 mm². A ratio of acoefficient of thermal expansion of the substrate (e.g., CTE_(sub)) to acoefficient of thermal expansion of the integrated circuit die (e.g.,CTE_(die)) is at least about 3:1.

Non-limiting example embodiments of the die 105 can include square orrectangular shaped dies, e.g., having areas of 400 mm² or greater. Asnon-limiting examples, the length and width (e.g., FIG. 1, L and W) ofthe die can about 26 mm and 16 mm, 24 mm and 19 mm, 20 mm and 20 mm, 25mm and 25 mm or 30 mm and 30 mm, respectively.

In some embodiments, to facilitate providing a high density of thesolder bumps per unit area of the die, an average diameter (e.g., FIG.1, diameter 146) of the one or more solder bumps 115 can be a value in arange from about 10 to 200 microns, and in various embodiments, have anaverage diameter value in a range from about 10 to 20, 20 to 40, 40 to60 or 60 to 80, 80 to 100, or 100 to 150 microns. In some suchembodiments, the bump pad diameter (e.g., FIG. 1, diameter 147) canrange from 1 to 1.5 times the diameter of the solder bump (e.g., 10 to300 microns).

In some embodiments, the corner region 120 has a separation distance 150from a center 152 of the integrated circuit die major surface 110 thatis equal to or greater than about 40 percent of a diagonal distance 115of the major surface 110. In various embodiments, the separationdistance 150 can be a distance value in a range of about 40 to 50, 50 to60, 60 to 70, 70 to 80 or 80 to 90 percent of the diagonal distance 115.

In some embodiments, the one or more solder bumps 115 are part of anarray (e.g., a ball grid array) on the major surface 110, the solderbumps of the array individually bonded to a corresponding array of thebump pads 115 on the substrate surface 130, e.g., to form an array ofthe bond joints 202, as part of flip chip bonding processes familiar tothose skilled in the pertinent arts.

In some embodiments, the one or more solder bumps 115 can include anunder bump metallization (UBM) region 205, the UBM region 205 locatedbetween a redistribution metal layer 210 and a pillar layer 215including copper, the pillar layer 215 located over a layer 220including nickel and a solder layer 230 (e.g., lead free solder). Oneskilled in the pertinent art would be familiar with various types ofthin film UBM stacks to provide an electrical and mechanical connectionbetween the solder bump 105 and bump pad 115 and a barrier to limit theundesired diffusion of copper atoms to the die 105.

As further explained in the context of FIG. 3, the IC packages 100 ismanufactured such that the solder bump 105 and bump pad 115 aresubstantially aligned with each other through the bond joint 202 at analignment reflow temperature. For instance, in some embodiments, each ofthe bond joints 202 has an alignment such that a center line 240 of thesolder bump 115 and a center line 245 of the bump pad 135 are laterallydisplaced by a separation distance 250 that is less than about one-halfa diameter 255 of the solder bump 115, and in some embodiments, lessthan one-third or less than one-quarter or less than one-tenth thediameter 255 of the solder bump 115.

The bond joints 202 formed between substantially aligned solder bumpsand bump pads facilitates the bond joint 202 maintaining its integrityfollowing a thermal cycling test. The term integrity, as used herein,means that visual examination of the bond joint reveals no signs ofphysical cracks, and, that electrical measurements of functionalityreveals no loss in electrical continuity through the bond joint. Oneskilled in the pertinent art would be familiar with standardize testconditions to assess the integrity of the bond joint, e.g., using testconditions such as specified using spec JESD22-A104D (Joint ElectronTube Engineering Council, JEDEC, Arlington, Va.). As a non-limitingexample, some embodiments follow a thermal cycling test that includetemperature cycling from −40° C. to 125° C. for 1000 cycles with a rateof about 2.5 to 3 cycles per hour. For example, in some embodimentsafter such a thermal cycling test, the bond joints 202 show no physicalsigns of cracks and an electrical conductivity through the bond jointsis substantially the same (e.g., within ±10 or ±1 percent, in someembodiments) as the electrical conductivity prior to the thermal cyclingtest.

As noted above, the coefficient of thermal expansion of the substrate(CTE_(sub)) and the coefficient of thermal expansion of the die(CTE_(die)) are substantially different from each other, e.g., having aCTE_(sub):CTE_(die) ratio of about 3:1 or greater in some embodiments.For instance, in some embodiments the die can be composed of aninorganic semiconductor material (e.g., silicon) having a CTE_(die)value in a range from about 2.5 to 3.5 ppm/° C. For instance, in someembodiments, the substrate can be composed of a composed of an organicmaterial (e.g., glass fiber reinforced epoxy or phenolic resins) havinga CTE_(sub) value in a range from about 10 to 16 ppm/° C.

In some embodiments, the substrate 125 is a printed circuit board, andincludes multiple metal vias connected to the bump pads, the metal viaslocated in interconnection layers of the substrate 125.

In some embodiments, the bump pads of the substrate are C4 pads(controlled collapse chip connection pads) as familiar to those skilledin the pertinent art.

In various embodiments, the package 100 can be configured as a datacenter/server device package, a system-on-a-chip (SoC) package, agraphical processing unit device package, central processing unitpackage, an AI machine learning device package, or combinations thereof.

Embodiments of the package can be used in high temperature (e.g., up toabout 125° C. in some embodiments) and/or vibrating environments, wherehaving bond joints with high integrity would be advantageous.Non-limiting examples include IC packages adapted for use in a motorizedvehicle, including an autonomous vehicle, e.g., a SoC package to controla vehicle's operation, such as an automobile including an autonomouslydriven automobile.

Another aspect of the disclosure is a method of manufacturing anintegrated circuit package. FIG. 3 presents a flow diagram of exampleembodiments of a method 300 of manufacturing an IC package according tothe principles of the disclosure such as any embodiments of the ICpackage 100 disclosed in the context of FIGS. 1 and 2.

FIGS. 4A-4D show cross-sectional views, analogous to that show in FIG.2, of example embodiments of test and production dies and substrates atselected stages of the method embodiments as discussed in the context ofFIG. 3.

With continuing reference to FIGS. 1-4D throughout, embodiments of themethod 300 includes providing a test one of an integrated circuit diehaving a major surface and a solder bump located on the major surface(step 310, e.g., a test one of die 105 a with a test solder bump 115 onsurface 110), and, providing a test one of a substrate having a surface,the surface including a bump pad located thereon (step 315, e.g., a testbump pad 135 on surface 130 of a test one of substrate 125 a). The bumppad is at a location on the surface 130 for alignment and bonding to thesolder bump when the die is positioned at a target mounting location(e.g., a flip-chip mounting location) relative to the substrate with thedie and the substrate at room temperature.

The method 300 further includes determining a shrinkage factor (SF)(FIG. 3, step 320) for the bump pad according to the formula:SF=1−(ΔD_(offset)/D_(rt)). D_(rt) is a distance between a center of thedie (e.g., die center 152, FIG. 4A) and the center of the solder bump(e.g., solder bump center 240, FIG. 4A) with the die and the substratealigned with each other at room temperature (e.g., about 25° C.).ΔD_(offset) is the absolute value of D_(substrate reflow) minusD_(pad reflow) (e.g., |D_(substrate reflow)−D_(pad reflow)|), whereD_(substrate reflow) is a lateral offset distance between the center ofdie and D_(pad reflow) is an offset distance between the center of thedie and the solder bump, with the die positioned at the target mountinglocation relative to the substrate, and with the test die and the testsubstrate at an alignment reflow temperature for bonding the solder bumpto the bump pad.

For instance, as shown in FIG. 4B, at elevated temperatures, such asduring a heat reflow cycle applied to the test die 105 a and testsubstrate 125 a, both the die and substrate expand, but, the substrateexpands to a greater extent than the die because CTE_(substrate) isgreater than CTE_(die). Consequently, the center 245 of the test bumppad 135 a becomes offset from the center 240 of the test solder bump 115a at the elevated temperature. The extent of the offset is used as partof determining the SF using the above formula, and the SF, in turn, isapplied to determine a re-location of the bump pad formed on aproduction substrate so that the solder bump and solder pad will bealigned at the elevated temperature.

The method 300 further includes forming another of the bump pad on thesurface of a production one of the substrate (FIG. 3, step 340, e.g.,FIG. 4C production bump pad 135 b on production substrate 125 b). Thelocation of the bump pad on the production substrate is offset by theshrinkage factor multiplied by the bump pad location on the testsubstrate such that a lateral distance between a center of the die andthe pad bump on the production substrate at room temperature equalsSF×D_(rt).

For instance, when the test die is positioned at the target mountinglocation relative to the test substrate, such as illustrated in FIG. 4A,the lateral distance between the center 152 of the test die 105 and thetest bump pad 135 a on the test substrate 125 a equals D_(rt) becausethe aligned centers 240, 245 of the test solder bump 240 and test bumppad 245 are concentric with each other.

Multiplying D_(rt) by SF provides a re-positioned location of theproduction bump pad on the production substrate, relative to the testsubstrate, such that at the elevated alignment reflow temperature, theproduction bump pad and the production solder bump will be aligned andthereby able to form a bond joint with a desired level of integrity,such as disclosed elsewhere herein in the context of FIG. 1-2.

For instance, as illustrated in FIG. 4C, at room temperature, thelateral distance between the center 152 of the production die 105 b andthe production bump pad 135 b on the production substrate 125 b isD_(rt) multiplied by SF. The re-location of the production bump pad 135b provides a compensation for the greater expansion of the substratethan the die during a heat reflow cycle. Because the re-location of theproduction bump pad 135 b on the production substrate 125 b is laterallycloser to the center of the die, this relocation on the productionsubstrate is referred to as being shrunken as compared to the positionof the test bump pad 135 a on the test substrate 125 a. The degree ofsuch shrinkage is defined by the value of the shrinkage factor, SF. Notethat the position of the production solder bump 115 b on the productiondie 105 b is not relocated and not different from the position of thetest solder bump 115 a on the test die 105 a.

The method 300 further includes positioning the production one of theintegrated circuit die 105 b and the production substrate 125 b suchthat the production one of the solder bump 115 b (re-positioned such asdisclosed above) on the major surface 110 of the production integratedcircuit die 105 b faces the production substrate surface 130 at thetarget mounting location (FIG. 3, step 350).

The method 300 further includes forming a bond joint between theproduction solder bump 115 b and the production bump pad 135 b, theforming including applying a heat reflow cycle to the production die 105b and the production substrate 125 b (FIG. 3, step 360, e.g., FIG. 4D,bond joint 202).

To further illustrate aspects of the method 300, consider themanufacture of an example IC package including a die with a foot printarea of 500 mm² (e.g., FIG. 1, L=25 mm W=20 mm) and with a solder bumpcenter 240 located about 0.45 mm and 0.45 mm away from a corner of thedie (e.g., FIG. 1, die corner 160), e.g., with L and W coordinates of12.05 mm (12050 μm) and 9.55 mm (9550 μm), respectively, with respect tothe center 152 of the die designated as having L and W coordinates of 0mm and 0 mm. When the substrate is at its target mounting locationrelative to the substrate, a corresponding bump pad center 245 of thesubstrate is aligned with the bump pad center 240 at room temperature(25° C.). The bump pad center has the same lateral L and W coordinatesof 12.05 mm and 9.55 relative to the die center and therefore thecorresponding D_(rt) for the solder bump and bump pad both equal 15.3755mm (e.g., √(12.05²+9.22²) or 15375.5 μm). Further assume that CTE_(die)and CTE_(substrate) equal 2.6 and 12.0 ppm/° C. respectively,corresponding to a CTE mismatch (ΔCTE) of 9.4 ppm° C.

For such a package, at an alignment reflow temperature of 230° C. (e.g.,ΔT=205° C. relative to a room temperature of 25° C.) the die expandsaccording to its CTE_(die) and the solder bump center correspondinglyexpands to L and W coordinates of 12056.4 and 9555.1 μm, respectively,and therefore D_(pad reflow) for the solder bump equals 15383.7 μm. Thesubstrate expands according to its CTE_(substrate) and the bump padcenter correspondingly expands to L and W coordinates of 12079.6 and9573.5 μm, respectively. Therefore D_(substrate reflow) for the bump padequals 15413.3 μm. Therefore ΔD_(offset) equals 29.6 microns (e.g.,|15413-15384|,) and SF equals 0.998073. Consequently, for a productionsubstrate of the example package the bump pad will be relocated suchthat the lateral distance between a center of the die (positioned at itstarget mounting location relative to the substrate) and the bump pad onthe production substrate at room temperature equals 15345.9 μm (e.g.,SF×D_(rt)=0.998073×15375.5 μm).

Alternatively ΔD_(offset) can be calculated by first calculating L and Woffsets (L_(off) and W_(off) respectively) using the formulas:L_(off)=ΔT×ΔCTE×L_(rt)×10⁻⁶ and W_(off)=ΔT×ΔCTE×W_(rt)×10⁻⁶ where L_(rt)and W_(rt) are the L and W coordinates of the solder bump center at roomtemperature in microns (e.g., 12050 μm and 9550 μm), respectively, andthen calculating ΔD_(offset) using the formula ΔD_(offset)=√(L_(off)²+W_(off) ²) (e.g., 29.6 microns=√(23.22²+18.40²)).

As demonstrated by the above example, the re-positioning of someembodiments of the bump pad center relative to the die center on aproduction substrate compared to a test substrate at room temperaturecan result in a surprisingly large offset distance of about 30 μm (e.g.,ΔD_(offset)=15345.9 μm-15375.5 μm). In other embodiments, depending onthe position of the solder bump of the die and corresponding bump pad onthe substrate, the ΔT, and, the ΔCTE, the offset distance ΔD_(offset)can vary widely, e.g., ranging from 1 or 2 μm to 50 or 70 μm. Forexample continuing with the same example IC package, for solder bump andcorresponding bump pad locations having L and W coordinate locations of1000 and 1000, 5000 and 5000 or 10000 and 10000 μm relative to the diecenter, ΔD_(offset) would equal about 1.36, 6.81 and 13.6 μm,respectively. In contrast, for L and W coordinate locations of 40000 and40000 μm or 50000 and 50000 μm, ΔD_(offset) would equal about 54.5 and68.1 μm, respectively.

Additionally, the relative advantage of applying the method 300 tore-position the bump pad center, e.g., to facilitate providing a bondjoint with improved integrity, will also depend upon the relativediameters of the solder bump and bump pad. For instance, for solderbumps and bump pads having diameters in a range of 10 to 20 μm,re-positioning the bump pad center by a ΔD_(offset) of about 2, 4 or 6μm may substantially improve the integrity of the subsequently formedbond joint, while a similar degree of re-positioning of solder bumps andbump pads having diameters in a range of 90 to 100 μm may have a smallereffect on improving the integrity of the bond joint, although integrityis still expected to improve.

Herein, the alignment reflow temperature refers to a temperature wherethe solder bump and bump pad are aligned with each other to form thebond joint during the heat reflow cycle, e.g., due to the application ofthe shrinkage factor (SF) to re-position the bump pad location on theproduction substrate. In some embodiments of the method 300, thealignment reflow temperature at which to determine the shrinkage factormay be evaluated empirically, e.g., by performing the method 300 on aseries of different test and production dies and substrates usingdifferent prospective SF values and then evaluating the integrity of thebond joints thus formed.

In some embodiments, for instance, the alignment reflow temperatureoccurs at a temperature that is less than a maximum temperature duringthe heat reflow cycle (e.g., about 260° C. in some embodiments) andgreater than a melting temperature of the solder bump (e.g., about 220°C. in some embodiments for some embodiments of solder bumps composed oflead free solder). In some embodiments, the alignment reflow temperatureoccurs at a temperature that is in a range of about 20 to 40° C. lowerthan a maximum temperature during the heat reflow cycle

In some embodiments of the method 300 the heat reflow cycle includeselevating the temperature of the substrate and die from room temperature(about 25° C.) to about 250 to 270° C. (about 260° C. in someembodiments) and then reducing the temperature back to room temperatureover a cycle period ranging from 5 to 60 seconds. One skilled in thepertinent art would be familiar which various heat reflow cycles asappropriate for different combinations of dies, substrates, solder bumpand bump pad compositions and combinations.

The method 300 can be applied to manufacture any sized combination ofdie and substrate, but may be particularly advantageous when the majorsurface of the integrated circuit die has a footprint area (perimeter145) of at least about 400 mm² and/or when a ratio of CTE_(sub) toCTE_(die) is at least about 3:1 and/or the solder bump is in a perimeterregion of the die such as a corner region such as discussed in thecontext of FIGS. 1-2.

Based on the disclosed method, one skilled in the pertinent art wouldappreciate how the method 300 could be repeated for each of the solderbumps and corresponding bond pads on the die and substrate,respectively, to re-position the entire array of bond pad locations on aproduction substrate for improved alignment and bond joint integrity.For instance, in some embodiments the production solder bump and theproduction bump pad are part of an array of solder bumps andcorresponding bump pads that are bonded to each other as part of a flipchip bonding process that includes the application of the heat reflowcycle.

Those skilled in the art to which this application relates willappreciate that other and further additions, deletions, substitutionsand modifications may be made to the described embodiments.

What is claimed is:
 1. An integrated circuit package, comprising: anintegrated circuit die having a major surface and one or more solderbumps located on the major surface in at least one corner region of themajor surface; and a substrate having a surface, the surface includingbump pads thereon, wherein: the major surface of the integrated circuitdie faces the substrate surface, the one or more solder bumps are bondedto individual ones of the bump pads to thereby form a bond joint, themajor surface of the integrated circuit die has a footprint area of atleast about 400 mm², and a ratio of a coefficient of thermal expansionof the substrate (CTE_(sub)) to a coefficient of thermal expansion ofthe integrated circuit die (CTE_(die)) is at least about 3:1.
 2. Thepackage of claim 1, wherein an average diameter of the one or moresolder bumps is a value in a range from about 10 to 200 microns.
 3. Thepackage of claim 1, the corner region has a separation distance from acenter of the integrated circuit die major surface that is equal to orgreater than about 40 percent of a diagonal distance of the majorsurface.
 4. The package of claim 1, wherein the one or more solder bumpsare part of an array on the major surface, the solder bumps of the arrayof solder bumps individually bonded to a corresponding array of the bumppads on the substrate surface to form an array of the bond joints. 5.The package of claim 1, wherein the one or more solder bumps include anunder bump metallization region, the under bump metallization regionlocated between a redistribution metal layer and a pillar layerincluding copper, the pillar layer located over layer including nickeland a solder layer.
 6. The package of claim 1, wherein each of the bondjoints has an alignment such that a center line of the solder bump and acenter line of the bump pad are laterally displaced by a separationdistance that is less than about one-half a diameter of the solder bump.7. The package of claim 1, wherein the IC die is composed of aninorganic semiconductor material having a CTE_(die) value in a rangefrom about 2.5 to 3.5.
 8. The package of claim 1, wherein the IC die isa silicon die.
 9. The package of claim 1, wherein the substrate iscomposed of organic material having a CTE_(sub) value in a range fromabout 10 to
 16. 10. The package of claim 1, wherein the substrate is aprinted circuit board, and includes multiple metal vias connected to thebump pads, the metal via located in interconnection layers of thesubstrate.
 11. The package of claim 1, wherein the bump pads includes aC4 pad.
 12. The package of claim 1, wherein the package is a datacenter/server device package, a system-on-a-chip (SoC) package, agraphical processing unit device package, central processing unitpackage, an AI machine learning device package, or combination thereof.13. The package of claim 12, wherein the package is adapted for use in amotorized vehicle.
 14. The package of claim 1, wherein locations of thebump pads on the substrate are offset by a shrinkage factor multipliedby test bump pad locations on a test substrate such that a lateraldistance between a center of a test integrated circuit die and the bumppad on the test substrate at room temperature equals SF×Drt, wherein:SF=1−(ΔD _(offset) /D _(rt)), D_(rt) is a distance between a center ofthe test die and a center of the solder bump with the solder bump andthe bump pad aligned with each other and the test die at a targetmounting location at room temperature,ΔD _(offset) =|D _(substrate reflow) −D _(pad reflow)|,D_(substrate reflow) is a lateral offset distance between the center ofthe test die, and D_(pad reflow) is an offset distance between thecenter of the test die and the solder bump, with the test die positionedat the target mounting location and with the test die and the testsubstrate at an alignment reflow temperature for bonding the solder bumpto the bump pad.